1. Field of the Invention
The invention relates to a memory controller, and more particularly to a low power DDR memory controller.
2. Description of the Related Art
Generally, in a double data rate (DDR) memory system, such as a DDR dynamic random access memory (DRAM) system, each of a main die comprising a memory controller and a memory device comprising a DRAM device has one set of two terminal resistors coupled in series between a respective operation voltage and ground voltage for one input/output (I/O) pin of a bi-directional transmitter, and the joint point between the two terminal resistors is coupled to the I/O pin. For each of the main die and the memory controller, a respective on-die termination (DOT) voltage is equal to a half of the respective operation voltage. In this structure, static power dissipation occurs. For example, in a DRAM system with a series DDR3 1.5V/240Ω, there is a static current of 6.25 mA per one bit for each of the read and write paths. In a DRAM system with a series DDR2 1.8V/30Ω, there is a static current of 6 mA per one bit for each of read and write paths. In recent years, low power is required for DRAMs. Thus, static current induced in a DRAM system may be decreased to achieve the low power requirement.
Thus, it is desired to provide a low power memory controller which induces a low static current.